| |
TABLE OF CONTENTS
APPLICATION NOTES FOR THE ANADYNE, INC. L-17D©
LOGARITHMIC VIDEO AMPLIFIER
|
| |
| 1. |
INTRODUCTION |
3 |
| 2. |
GENERAL ARCHITECTURE |
4 |
| |
- Fig. 1(a) L-17D Block Diagram
- Fig. 1(b) L-17D Pinout Diagram
- Fig. 2(a) A1 Layout
- Fig. 2(b) A2 & A3 Layouts
- Fig. 2(c) Logging Section Layout
- Fig. 2(d) Output Section Layout
- Fig. 3 L-2010 Die Image, with Pad Labels |
4
5
6
7
8
9
10 |
| 3. |
NOTES FOR PRIOR L-17C USERS |
11 |
| |
Major Differences between the L-17C and the L-17D
Pin-by-Pin Discussion, and Comparison to the L-17C |
11
14 |
| 4. |
SAMPLE DATA |
15 |
| |
- Figs. 4(a), 4(b) Typical L-17D Pulse Wave Forms
- Fig. 5 L-17D Transfer Function Data
- Figs. 6(a-d) L-2010 Hybrid Pulse Wave Forms
- Fig. 7 L-2010 Hybrid Wide-Pulse Ladder |
15
16
17
18 |
| 5. |
PC17D-2 TEST BOARD |
19 |
| |
- Fig. 8(a) PC17D-2 Top
- Fig. 8(b) PC17D-2 Bottom
- Fig. 8(c) PC17D-2 Layout |
20
21
22 |
| 6. |
SETTING UP THE L-17D |
23 |
| |
- A1: (PINS 1,2,3,4,6,34,35)
- A2: (PINS 29,31,32,33)
- A3: (PINS 24,25,26,28) |
24
25
25
|
| |
- LOGGING SECTION |
26 |
| |
(PINS 8,9,10,11,13,15) |
|
| |
- OUTPUT AMPLIFIER |
26 |
| |
(PINS 16,17,18,19,20,21) |
|
| |
- SPEEDING UP & SLOWING |
27 |
| |
DOWN THE L-17D |
|
| |
- TEMPERATURE COMPENSATION |
28 |
| |
- Figs. 9(a-b) TEMP COMP DIAGRAMS |
29 |
| |
- OVERCOMING PARALLEL SHIFT OF LOG CURVES
- BIPOLAR OPERATION
|
30
31 |
| 7. |
SOME COMPONENT VALUES FOR THE PC17D-2 |
32 |
| |
- Fig. 10 Pulse Response |
33 |
| 8. |
PACKAGING OF THE L-17D |
34 |
| |
- Fig. 11 BONDING DIAGRAM
- Fig. 12 L-17D HOUSING DRAWING
- Fig. 13 PACKAGE LID DRAWING
|
34
35
36 |
| 9. |
RELIABILITY OF THE L-2010 AND THE L-17D |
37 |
|
| |
2 February 20, 2008 |
|
|
